In the manufacture of semiconductive devices, the steps of depositing layers and etching selected portions of layers which constitute the final chip in many cases employ ion beam and/or plasma processes. However, processes such as plasma deposition, plasma etching and ion implantation contribute to charging damage, leakage paths and/or gate oxide blow out. In particular, during plasma processes, the semiconductor wafer surface becomes negatively charged causing a potential drop across the wafer because the surface which the wafer rests on is at a different potential than the plasma potential. Typically, electrically floating surfaces within a plasma acquire a negative charge due to the higher mobility of electrons as compared to positively charged ions.
This potential drop can result in wafer charging, leakage paths, and breakdown of dielectric layers (see FIG. 1). This same problem occurs when employing ion beam techniques since such result in a positive charge on the wafer surface due to ion bombardment from the ion beam.
The problem due to the potential drop across the wafer is particularly pronounced when dealing with relatively thin dielectric layers such as about 40 to about 50 angstroms which are especially sensitive to being damaged. For instance, see Gabriel, "Measuring and Controlling Gate Oxide Damage from Plasma Processing", Semiconductor International, July 1997, pp. 151-156. In fact, in view of the significance of this problem of gate oxide damage, in 1996 the American Vacuum Society, the IEEE/Electron Devices Society and the Japan Society of Applied Physics sponsored the first International Symposium on Plasma Process-Induced Damage.
It would therefore be desirable to provide a method to compensate for or eliminate this potential drop across the wafer or at least to minimize the possible detrimental effect attributed to this problem.